GitHub intelligence
chipsalliance/
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Observed OCT 8, 2026 · 00:08 UTC
Facts
- Language
- C++
- License
- other
- Created
- NOV 7, 2019
- Last push
- Last release
- GitHub
- chipsalliance/verible ↗
Measurements
- Stars
- 1,950
- Forks
- 309
- 7D change
- Collectingfrom OCT 9
- 30D change
- Collectingfrom NOV 1
- 90D change
- Collectingfrom DEC 31
- Velocity
- Collectingfrom OCT 16
- Acceleration
- Collectingfrom OCT 23
- Trajectory
- Collectingfrom OCT 16
- Trending percentile
- Collectingfrom OCT 16
Categories
Technologies
Not linked to any curated technology.
Star history
Daily history began OCT 2. The chart appears after 7 days. 1 observed day shown.
Observed days (1)
| Day | Stars | Forks |
|---|---|---|
| OCT 2 | 1,950 | 309 |