GitHub intelligence

eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Observed OCT 8, 2026 · 00:08 UTC

Facts

Language: Tcl
License: other
Created: FEB 15, 2020
Last push: 3mo ago
Last release: 3mo ago
GitHub: eugene-tarassov/vivado-risc-v ↗

Measurements

Stars: 1,098
Forks: 252
7D change: Collectingfrom OCT 9
30D change: Collectingfrom NOV 1
90D change: Collectingfrom DEC 31
Velocity: Collectingfrom OCT 16
Acceleration: Collectingfrom OCT 23
Trajectory: Collectingfrom OCT 16
Trending percentile: Collectingfrom OCT 16

Categories

Embedded, IoT & Hardware (primary)

Technologies

MemberLinuxTagged linux

Star history

Daily history began OCT 2. The chart appears after 7 days. 1 observed day shown.

Observed days (1)

Day	Stars	Forks
OCT 2	1,098	252